`define SS_0 7'b1111110
`define SS_1 7'b0110000
`define SS_2 7'b1101101
`define SS_3 7'b1111001
`define SS_4 7'b0110011
`define SS_5 7'b1011011
`define SS_6 7'b1011111
`define SS_7 7'b1110000
`define SS_8 7'b1111111
`define SS_9 7'b1111011

module sseg(bin,segs);
  input [3:0] bin;
  output [6:0] segs;
  reg [6:0] segs;

  always @(*) begin
      case(bin)
	  0:segs=`SS_0;
	  1:segs=`SS_1;
	  2:segs=`SS_2;
	  3:segs=`SS_3;
	  4:segs=`SS_4;
	  5:segs=`SS_5;
	  6:segs=`SS_6;
	  7:segs=`SS_7;
	  8:segs=`SS_8;
	  9:segs=`SS_9;
	  default: segs=7'b0000000;
      endcase
  end
endmodule


//-----
//invsseg---如果输入信号，即输入七段码有效，则输出对应的二进制
//segs:七位段码
//bin:二进制输出
//valid:如果输入七段码有效，则为真
module invsseg(segs,bin,valid);
  input [6:0] segs; 
  output [3:0] bin;
  output valid;
  reg [3:0] bin;
  reg valid;
  always @(*) begin
      case(segs)
	  //信号拼接{valie,bin}
	  `SS_0: {valid,bin} = 5'h10;
	  `SS_1: {valid,bin} = 5'h11;
	  `SS_2: {valid,bin} = 5'h12;
	  `SS_3: {valid,bin} = 5'h13;
	  `SS_4: {valid,bin} = 5'h14;
	  `SS_5: {valid,bin} = 5'h15;
	  `SS_6: {valid,bin} = 5'h16;
	  `SS_7: {valid,bin} = 5'h17;
	  `SS_8: {valid,bin} = 5'h18;
	  `SS_9: {valid,bin} = 5'h19;
	  0: {valid,bin} = 5'h00;
	  default: {valid,bin} = 5'h01;
      endcase
  end
endmodule


